Article By : Don Scansen
The papers from the upcoming VLSI Know-how Symposium counsel there’s some settlement on common course, however little settlement on terminology.
The VLSI 2021 Symposia (plural, since there’s a semiconductor expertise observe and a circuits & programs observe) might be a digital occasion held the week of June 12. In regular instances, VLSI alternates between Hawaii and Japan. This 12 months’s “location” is Japan.
The theme is “VLSI Techniques for Way of life Transformation.”
The 2021 Circuits Symposium Chair, Ken Takeuchi, made these feedback in his invitation:
“Even when Covid-19 is recovered sooner or later, our society could face the drastic life-style transformation. Individuals could come to work in additional distant manners and are much less more likely to bodily transfer for each private and enterprise points. The microscopic life-style change of particular person individuals in addition to macroscopic social construction change corresponding to the corporate group, metropolis planning and transportation could happen. On the 2021 Symposium, contemplating these life-style transformations, we’ll focus on how state-of-the-art VLSIs can contribute to such life-style and heath transformations.”
The primary expertise symposium plenary hits instantly on the pandemic with “Pandemic Challenges, Know-how Solutions” introduced by Siyoung Choi, president and common supervisor of Foundry Enterprise at Samsung. Though it has introduced the trade with challenges, the pandemic has offered one of many largest booms for the semiconductor enterprise, and Samsung ought to have an attention-grabbing perspective on making use of the teachings of the final 12 months to its foundry enterprise.
Between the nanosheets
With so few gamers concerned at superior nodes, one would possibly assume that there might be much less range within the expertise view. As we’re down to 2 producers presently on the most superior 5 nm manufacturing nodes (Samsung and TSMC) there’s some fact to that time.
However, nonetheless, expertise change for the entrance finish of the manufacturing movement is coming quicker than ever as finFETS get set to retire. Two applied sciences are on the horizon because the trade must scale past the finFET.
The preliminary expertise past the finFET would be the nanosheet transistor. That is broadly a part of an idea that will even be described as gate throughout or GAA. Nanowire is one other time period that readers could also be aware of which is barely a barely totally different taste of nanosheet.
Nanosheet expertise receives a full session (together with together with design expertise co-optimization). in Session 15 and the plainly titled Nanosheet and DTCO.
IBM, Nvidia, Qualcomm, and Samsung are all represented on the expertise co-optimization aspect, however the nanosheet papers on this session are all from academia.
The opposite papers on GAA expertise are scattered across the convention. A pair are of explicit word.
Jin Cai from TSMC will current CMOS System Know-how for the Subsequent Decade as one of many modules of the primary VLSI quick course Superior Course of and System Know-how Towards 2nm-CMOS and Rising Reminiscence). Cai intends to debate present finFET expertise and provides some roadmap view to the nanosheet machine with TSMC’s imaginative and prescient. TSMC has held off for the following technology, as a substitute extending finFET for the three nm node. Judging from a equally titled presentation from IEDM 2019, the fabric could particularly embrace 2D materials channel gadgets (extra on this later).
The second module of the quick course is from IMEC: Nanosheet System Architectures to Allow CMOS Scaling in 3nm and Past: Nanosheet, Forksheet and CFET. This quick course subject might be introduced by IMEC’s director of Logic CMOS System Know-how Program, Naoto Horiguchi.
With Samsung set to launch its MBCFET (multi-bridge channel FET) later this 12 months, one ought to anticipate emphasis on this expertise. (Sure, MBCFET is yet one more time period, the Samsung model for nanosheet transistors.) Samsung is represented elsewhere within the convention, however doesn’t have an entry for the MBCFET.
Its director for logic CMOS improvement launched the subject as a part of the gate throughout roadmap within the quick course, and IMEC experiences the particular developments in forksheet transistors within the second of the Know-how papers periods. Forksheet FETs for Superior CMOS Scaling: Forksheet-Nanosheet Co-Integration and Twin Work Perform Steel Gates at 17nm N-P House examines the combination of N- and P-channel gadgets to advertise the world scaling benefits of the forksheet construction.
After the silicon and silicon-germanium nanosheet variants run out of steam, the trade will transfer to a essentially new class of channel supplies.
2D or not 2D…
2D channel transistors will change nanosheet gadgets within the subsequent decade or so. Some landmark research of those gadgets have been examined in EE Times recently. As a extra futuristic method, this expertise options extra prominently at VLSI 2021.
There are 5 2D supplies papers accepted to this 12 months’s convention, primarily within the third expertise session – Future Logic Units.
IMEC is properly represented with two papers masking WS2 expertise within the logic machine session. The primary is a tool paper detailing gate scaling for twin gate WS2 transistors.
The second IMEC paper strikes nearer to the industrial feasibility of the 2D materials idea by discussing course of yield and uniformity for 300 mm wafers. The important thing level is the potential as integration of those transistors into backend of line course of for monolithic 3D chips.
On that word, a analysis paper from Taiwan (Nationwide Yang Ming Chiao Tung College and TSRI) will current findings on monolithic 3D integrations for 2D supplies. The summary gives a possibility to spotlight some acronmyms that will pop up. Every time I’m tempted to truncate “2D materials channel transistor” to easily 2D or 2D transistor, I hesitate as a result of this harkens again to pre-finFET days. Maybe, I’m simply simply confused.
The NYCU-TSRI summary gives us 2DM and M3D. These might not be the primary appearances of the acronyms, however there’s simple efficency in “M3D-2D electronics” because the authors describe future monolithic 3D integration of 2D supplies channel transistors.
Common 2DM’s for research supply engaging processing temperatures for integration with commonplace backend metallic processing. It will likely be good to rememember these acronyms because the trade could also be adopting these applied sciences within the subsequent decade.
Though the logic session and the highlighted papers are attention-grabbing, one other 2DM paper escaped this session to land on the moderately blandly labeled Spotlight or session 2. However this follows on the heels of the plenaries and is supposed to seize the necessary papers for the convention.
Intel contributors will current Advancing Monolayer 2D NMOS and PMOS Transistor Integration From Progress to Van Der Waals Interface Engineering for Final CMOS Scaling within the third slot of the session.
For these fascinated with the way forward for CMOS and the machine roadmap a number of generations out, this paper is a should. Intel will examine progress on MoS2, WSe2, and WS2 together with the supplies development, gate oxide engineering, and contacts.
The GAA and 2DM papers are actually forward-looking, however not almost as futuristic as many to be discovered on the VLSI 2021 schedule. These transistor applied sciences have gotten well-established on the roadmap.
Get again to the place you as soon as belonged
Regardless of its give attention to a really mature expertise, there’s a paper that caught my eye. With the eye-watering device investments required for any semiconductor plant, squeezing further generations out of previous applied sciences has turn out to be a hallowed artwork within the enterprise.
In that vein, Utilized Supplies and IBM authors look at the extendability of twin damascene copper under 28 nm metallic line pitch. Dan Edelstein is within the writer checklist. That identify might be acquainted to these with as a lot as peripheral curiosity in copper interconnect expertise.
The AMAT/IBM researchers disclose two course of flows for 10nm hint width metals. A brand new spin with selective deposition of tantalum-nitride-barrier together with reflowed copper (Cu/R-TaN/SB), is proposed for subsequent technology cell chips. For top efficiency computing purposes, the analysis group suggests cobalt/copper composite.
Flavors of those supplies are presently in manufacturing, and their continued evolution and viability might be welcomed.
Don’t take this restricted preview as a sign of the breadth of deep expertise matters to be introduced at VSLI 2021. These are only a few excessive factors that caught my consideration, and people have been solely from the Know-how Symposium. That observe additionally gives reminiscence and ferroelectric transistors and many different attention-grabbing papers to be digested with the time saved on the standard journey time to this convention (at the very least for Europeans and North Individuals).
Many EE Occasions readers are possible extra within the Circuit Symposium, however that should wait for one more day.
This text was initially printed on EE Times.
Don Scansen has devoted over 20 years to supporting patent homeowners along with his technical experience in semiconductor expertise and associated fields. The IP consulting journey drives a eager curiosity within the information and tendencies which might be of curiosity to a broader viewers. He’s most readily discovered lurking on LinkedIn or reached by electronic mail at [email protected]